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Page 2 of 4
With this information we can now start to work with the GPIO registers:
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Offset
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Register Name
|
Description
|
|---|
|
0x000
|
GPIO0_STATUS
|
GPIO status
|
|
0x004
|
GPIO0_CTRL
|
GPIO control including function select and overrides
|
|
0x008
|
GPIO1_STATUS
|
GPIO status
|
|
0x00c
|
GPIO1_CTRL
|
GPIO control including function select and overrides
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|
… and so on down to
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|
0x0dc
|
GPIO29_CTRL
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GPIO control including function select and overrides
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You can see that there are two registers for each GPIO line from GPIO 0 to GPIO 27, one control register and one status register.
Each register has the same format for each GPIO line. For example, the status register is:
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|
Name
|
Description
|
Type
|
|---|
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31:30
|
Reserved
|
|
-
|
-
|
|
29
|
IRQTOPROC
|
Interrupt to processors, after override applied
|
RO
|
0x0
|
|
28
|
IRQCOMBINED
|
Interrupt to processors, after masking
|
RO
|
0x0
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27
|
EVENT_DB_LEVEL_HIGH
|
Debounced input pin is high
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RO
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0x0
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26
|
EVENT_DB_LEVEL_LOW
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Debounced input pin is low
|
RO
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0x0
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|
25
|
EVENT_F_EDGE_HIGH
|
Input pin has seen a filtered rising edge. Clear with ctrl_irqreset
|
RO
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0x0
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24
|
EVENT_F_EDGE_LOW
|
Input pin has seen a filtered falling edge. Clear with ctrl_irqreset
|
RO
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0x0
|
|
23
|
EVENT_LEVEL_HIGH
|
Input pin is high
|
RO
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0x0
|
|
22
|
EVENT_LEVEL_LOW
|
Input pin is low
|
RO
|
0x0
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21
|
EVENT_EDGE_HIGH
|
Input pin has seen rising edge. Clear with ctrl_irqreset
|
RO
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0x0
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20
|
EVENT_EDGE_LOW
|
Input pin has seen falling edge. Clear with ctrl_irqreset
|
RO
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0x0
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19
|
INTOPERI
|
Input signal to peripheral, after override applied
|
RO
|
0x0
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18
|
INFILTERED
|
Input signal from PAD, after filtering is applied but before override. Not valid if inisdirect=1
|
RO
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0x0
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17
|
INFROMPAD
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Input signal from PAD before override applied
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RO
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0x0
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16
|
INISDIRECT
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Input signal from PAD without filtering or override
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RO
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0x0
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15:14
|
Reserved
|
|
-
|
-
|
|
13
|
OETOPAD
|
Output enable to PAD, after override applied
|
RO
|
0x0
|
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12
|
OEFROMPERI
|
Output enable from selected peripheral, before override applied
|
RO
|
0x0
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|
11:10
|
Reserved
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|
-
|
-
|
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9
|
OUTTOPAD
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Output signal to PAD after override applied
|
RO
|
0x0
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8
|
OUTFROMPERI
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Output signal from selected peripheral, before override applied
|
RO
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0x0
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7:0
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Reserved
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|
-
|
-
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You can see that many of the 32 bits in the register are not used, but bit 9 is OUTTOPAD which is the final state of the GPIO line after register overrides have been applied.
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