Learn About RISC-V From Linux Foundation on edX
Written by Sue Gee   
Friday, 01 September 2023

The Linux Foundation has a new free course on the edX platform for those who would like to learn about, and experiment with, RISC-V. A verified track, to earn a certificate of completion, is also available.

Open Source Software Development Professional Certificate on edX

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Computer Architecture with an Industrial RISC-V Core [RVfpga] is a self-paced course that provides a practical introduction to using the open-standard RISC-V computer architecture based on a RISC-V system-on-chip (SoC) targeted to a field-programmable gate array (FPGA) and to different simulation tools.

The course provides hands-on experience with RISC-V computer architecture and teaches how to develop and compile C and RISC-V assembly code for the RVfpga SoC. Additionally, participants will learn how to configure the microarchitecture of the SweRV EH1 Core and test its different features using performance counters and industry-standard benchmarks. Finally, the course provides step-by-step instructions on how to execute programs on the Nexys A7 board or by using simulate programs such as: 

  • RVfpga-Whisper instruction set simulator (ISS)
  • Verilator-based RVfpga-ViDBo
  • RVfpga-Pipeline
  • RVfpga-Trace

According to Clyde Seepersad, General Manager of Training & Certification at the Linux Foundation:

“Learning how to use RISC-V to improve security, power consumption and performance of processors will enable people to help shape the future of computer architecture and ensure long-term career growth.”

  • Digital logic design
  • High-level programming (such as C programming)
  • Assembly programming
  • RISC-V instruction set architecture
  • Processor microarchitecture
  • Memory and input/output systems

It comprises ten chapters, each of which requires between 2 and 4 hours, which cover:

  • Installation and Initial Demonstrations
  • C Programming with the RVfpga SoC
  • RISC-V Assembly Programming with the RVfpga SoC
  • RISC-V Function Calls
  • Mixing C and Assembly Functions in a Program
  • Peripherals and Input/Output
  • I/O: 7-Segment Displays
  • I/O: Timers
  • Interrupts
  • RISC-V VeeR Core

There is a Final Exam for those on the Verified Track only.

Upon completion, learners should be able to use RISC-V to improve security, power consumption and performance of processors and help shape the future of computer architecture.

 RISC-V

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Last Updated ( Friday, 01 September 2023 )